According to the study by the inventor of the present invention, for example, the following technology is known in a non-volatile semiconductor storage device (non-volatile semiconductor memory).
In the field of a non-volatile semiconductor memory, in particular, in a flash memory, the capacity has been increased by reducing a cell size, and the data capacity of an application has also been increased from image and music to moving pictures. Accordingly, reading and programming rates capable of reading and programming large-capacity data without stress have been desired.
As an example of an overhead time at the time of reading, a read 1st access time is known. The read 1st access time is a time from an input of a data read command to an output of data for the first time. It is essential for the increase of a reading rate to reduce this read 1st access time. Of the read 1st access time, a time of reading data from the memory cell by a sense circuit accounts for a considerable ratio of 20%. This is one of large problems in increasing a reading rate, together with a time for activating an internal power supply circuit and a time for data transfer from a sense circuit to SRAM.
Furthermore, in a multilevel flash memory, in order to program at an intended threshold level, a verify read operation in which data in the memory cell is read at the time of each programming is repeated. For this reason, an increase in a reading rate is also essential for the achievement of an increase in a programming rate.
As a sense circuit of a flash memory, a circuit as shown in FIG. 11 is proposed in Japanese Patent Application Laid-Open Publication No. 7-105693 (Patent Document 1). Note that FIG. 11 is a drawing obtained by redrawing FIG. 1 and FIG. 2 of the Patent Document 1 from the inventor's point of view. FIG. 12 is a timing chart for describing the operation of the circuit of FIG. 11.